The present invention relates to the field of electronics, and more particularly, to an integrated memory comprising a plurality of memory cells arranged as a matrix with row and column addressing.
Reference may be made to the article xe2x80x9cA Survey of Circuit Innovations in Ferroelectric Random-Access Memoriesxe2x80x9d by Ali Sheikholeslami and P. Glenn Gulak, in Proceedings Of The IEEE, Vol. 88, No. 5, May 2000, which describes various types of memories. With reference to FIG. 23 of this article, a block diagram of a nonblowable, conventional ferroelectric memory comprising a matrix of memory cells is described therein.
The addressing is achieved via a column-wise bit line and a word line and a plate line per row. The word line of a row is arranged on one side of the memory cells of the row, while the plate line is arranged on the opposite side, adjacent to the word line of the next row. Each memory cell comprises a MOS transistor whose gate is linked to the word line, a drain linked to the bit line and a source linked to the capacitor. The other terminal of the capacitor is linked to the plate line.
In the field of blowable memories, one seeks to blow the capacitors of specified memory cells without harming the neighboring memory cells using a voltage greater than the normal operating voltage. By way of example, in a circuit whose normal operating voltage is 3.3 volts, a voltage of 6 volts is applied to one of the addressing lines, and the transistor of the memory cell to be blown is turned on. The other addressing line is set to 0 volts so that the capacitor experiences a voltage of 6 volts sufficient to blow it.
Stated otherwise, its characteristics are irretrievably modified. In known memories, the application of the blowing voltage results in excessive voltages across the terminals of the neighboring cells which could be damaged depending on the ratio of impedance between the capacitor and the transistor of each memory cell.
In view of the foregoing background, an object of the present invention is to provide a highly reliable blowable memory architecture so that the blowing of a memory cell does not negatively affect the other memory cells.
This and other objects, advantages and features according to the present invention are provided by a blowable memory device comprising a plurality of memory cells arranged as a matrix, with each memory cell comprising a transistor and a capacitor connected in series, and is linked to a bit line linked to the memory cells of a column, to a word line and to a third line. The gate of the transistor of a memory cell is linked to the word line. A third line is linked to the sources of the transistors of a row of memory cells, a bit line is linked to the capacitors of the transistors of a column of memory cells and a word line is linked to the transistors of a column of memory cells to form a word column so that the voltage seen by the transistor can be controlled via the word column and the third line.
In one embodiment of the invention, each third line is equipped with a driver for providing a voltage on the third line. In another embodiment of the invention, the memory device comprises a predecoding module connected to the drivers for providing a voltage on the third lines. Advantageously, each driver may provide a first voltage or a second voltage on a third line.
In another embodiment of the invention, the memory device comprises a decoding module for controlling a plurality of word columns and a decoding module for controlling a plurality of bit lines. The device may comprise at least one blowable type capacitor.
The device may comprise multiplexing means provided with a module per bit line and evaluation means. The modules selectively link a memory cell to the evaluation means. The evaluation means outputs a logic level corresponding to the impedance of the memory cell selected.
The invention also provides a method of blowing a capacitor of a memory cell, wherein each memory cell comprises a capacitor and a transistor connected in series. The method comprises providing a high voltage V1 on a terminal of the capacitor, an intermediate voltage V2 on the gate of the transistor, and a low, zero or negative voltage V3 on the source of the transistor. This is done while providing the high voltage V1 on the terminals of the capacitors of the memory cells of the same column, and an intermediate voltage V4 on the sources of the transistors of the other rows.
Thus, only the capacitor of the memory cell which one chooses to blow receives at its terminals a sizeable voltage, close to the difference V1xe2x88x92V3, while the elements of the other memory cells receive at their terminals voltages close to the normal operating voltage. Advantageously, the intermediate voltage V2 is imposed on the gates of the transistors of the same column. In one embodiment of the invention, the voltages V2 and V4 are equal. We can have V3=0 volts and V2 and V4 close to V1/2. More precisely, provision may be made for V2 and V4 to lie between 40 and 60% of the value of V1, and preferably between 50 and 60%. By way of example, V1 may be equal to 6 volts, V2 and V4 may be equal to 3.3 volts and V3 may be equal to 0 volts.